Power amplifiers are often used to amplify wideband signals or combinations of signals with high peak-to-average-power ratio (PAR). The amplifiers in these applications must then be able to repeatedly output relatively high power for very short periods, even though the output power is generated at a much lower average power level for the bulk of the time. In systems where the amplified signal generally comprises a random phase combination of many signals, without any dominating signals, the amplitude of the signal follows a Rayleigh distribution.
A conventional single-transistor power amplifier (for example a class B, AB, or F power amplifier) has a fixed radio-frequency (RF) load resistance and a fixed voltage supply. The bias in class B or AB amplifiers causes the amplifier's output current to have a form close to that of a pulse train of half-wave-rectified sinusoidal current pulses. The direct-current (DC) current consumed by the amplifier is therefore largely proportional to the RF output current amplitude (and voltage amplitude). Because the supply voltage is fixed, the DC power consumed by the amplifier is also proportional to the RF output current amplitude. The output power delivered by the amplifier, however, is proportional to the square of the RF output current amplitude. The amplifier's efficiency, i.e., the output power divided by the DC power, is therefore also proportional to the output amplitude. Consequently, the average efficiency of a conventional power amplifier is low when amplifying signals that on average have a low output amplitude (or power) compared to the maximum required output amplitude (or power), i.e., in high PAR applications.
It is well known that the outputs from multiple sub-amplifiers (each sub-amplifier comprising a transistor plus surrounding circuitry) may be combined with a passive network so that the resulting amplifier circuit operates in a Doherty mode or a Chireix mode of operation. These amplifier circuits use multiple transistors that are configured and controlled to exploit a passive output network interaction and combination. Such power amplifiers are much more efficient than conventional amplifiers for amplitude-modulated signals that have a high PAR, since they have a much lower average sum of output currents from the amplifier transistors. It will be appreciated that such a reduced average output current leads to high average efficiency.
The reduced average output current is obtained by using two amplifier transistors that influence the output voltages and currents of each other through a reactive output network that couples the amplifier transistors to the load. By driving the constituent amplifier transistors with suitable amplitudes and phases, the sum of RF output currents can be reduced at all output levels below the maximum output power level for the combination. Also, for these amplifiers the RF voltage at one or both transistor outputs is increased. The reduced RF output currents are essentially obtained by providing for a high trans-impedance from at least one transistor to the circuit's output, while maintaining the possibility of in-phase combining of all transistor outputs to obtain full output power. This reduced average output current means higher average efficiency, since the DC current is largely proportional to the RF current magnitude.
The field was generalized for two-transistor structures, for example by “Unified High-Efficiency Amplifiers”, published as International Patent Application WO 2003061115 A1 by the present Applicant. This publication discloses a two-stage high-efficiency amplifier with increased robustness against circuit variations, which can avoid tuning of the output network while providing for a radically increased bandwidth of high efficiency. This two-stage amplifier circuit includes a longer and a shorter transmission line respectively connecting the outputs of two amplifier transistors to a common output node, which in turn is coupled to a load, RLOAD. If the most wideband operation is desired, the lengths of the transmission lines are chosen such that the longer line has an electrical length of half a wavelength at center frequency, while the shorter line has an electrical length of a quarter wavelength at a nominal operating frequency for the circuit, e.g., at a center frequency of the operating band. The basic structure of such an amplifier is shown in FIG. 1.
The amplifier circuit 10 illustrated in FIG. 1 comprises a first amplifier 5 located in a first or “main” branch 1 of the amplifier circuit 10 and a second amplifier 6 located in a second or “auxiliary” branch 3 of the amplifier circuit 10. An output of the first amplifier 5 and an output of the second amplifier 6 are coupled to a common output 9 via respective first and second transmission lines 7 and 8. As mentioned above, the first and second transmission lines 7, 8 form a reactive output network that influences the operation of the first and second amplifiers 5, 6. The electrical length of the first transmission line 7 can be designed to be shorter than the electrical length of the second transmission line 8 (for example a quarter wavelength and a half wavelength, respectively, at a center frequency, as shown). In operation, an input signal 4 is received by the amplifier circuit 10, split by a signal component separator 2 and amplified by the first amplifier 5 and the second amplifier 6.
Amplifier circuit 10 has a wide bandwidth of high efficiency since the shorter/longer transmission lines 7, 8 of the output network interact with the transistors to form different kinds of amplifiers at different frequencies. Around a center frequency of operation the amplifier circuit 10 operates as a Doherty amplifier, and at ⅔ and 4/3 of that frequency the amplifier circuit 10 operates as a Chireix amplifier. A very wide (about 3 to 1) high-efficiency bandwidth is thus achieved in such an amplifier circuit 10 by devising an output network that has both suitable impedance transformation characteristics and full power output capacity over a wide bandwidth, together with a unified control system that allows high efficiency operation at all “modes” across that bandwidth. The amplifier circuit 10 of FIG. 1 therefore allows operation in between and outside the intrinsically narrowband Doherty and Chireix modes.
Further developments of the type of circuit shown in FIG. 1 include three basic expandable multi-transistor structures (and ways to drive them efficiently), such as those disclosed by the present applicant in U.S. Pat. No. 7,221,219, the entire contents of which are incorporated herein by reference. Amplifiers such as these, based on passive output network interaction structures, have the advantage of needing only basic RF network and signal modifications.
The reduced average output currents mentioned above also come with a drawback. The RF voltage swing at some transistors is increased, often to the maximum possible. This makes the amplifiers sensitive to resistive losses in a shunt path at the outputs of the transistors, i.e., between the drain and ground, since the loss power is proportional to the RF voltage swing squared. The most common causes of shunt loss are the small series resistance of the capacitance at the drain node, or coupling to a lossy substrate via the drain capacitance (Cds). These capacitively coupled losses often increase almost quadratically with frequency.
Another approach to improving the efficiency of a power amplifier is referred to as peak power reduction. This approach includes any of several techniques such as clipping, crest factor reduction (CFR), etc., which operate to reduce the peak power of a signal to be transmitted. With conventional single-transistor amplifiers this consequentially increases efficiency. Contrarily, multi-transistor amplifiers such as those described above can, with proper dimensioning, have efficiency almost independent of PAR.
Peak power reduction methods can in some systems reduce the peak power greatly, but while doing so they increase the noise level (EVM) in the signal. This decreases the signal to noise ratio, SNR, of the signal at the receiver, and will thus require a boost in average signal power to compensate for this. This increase in average power will increase both the DC power drawn and the power loss in the amplifier. For example, a commonly found compensatory 1-dB increase in average power increases the DC power drawn by 25% and thus decreases the “equivalent efficiency” to only 80% of the measured efficiency.
It is therefore beneficial to the system to use as little peak power reduction as possible. The ideal solution would be to have the possibility of high peak output power to cope with the peaks of high-PAR signals, while at the same time having high efficiency around the average power level.
Chireix-Doherty amplifiers have the potential of very high average efficiency for signals with high PAR. To achieve this, however, the transistors should have low shunt loss, i.e., a low resistive loss between the drain and ground nodes. Such transistors are generally more expensive than transistors with high loss. As mentioned above, the most common causes of shunt loss is the series resistance of the capacitance at the drain node, or coupling to a lossy substrate via the drain capacitance (Cds).